Maxime PELCAT

Research group on Embedded Architecture for Multisensing

Institut Pascal - CNRS UMR 6602
Institut Pascal
Avenue Blaise Pascal
63178 AUBIERE CEDEX
France

Dr. Maxime PELCAT

Associate professor
DREAM, ISPR

Maxime.Pelcat@-Code to remove to avoid SPAM-insa-rennes.fr
+ 33 2 23 23 82 83

Journal articles

2018

ref_biblio
M. Ammar, M. Baklouti, M. Pelcat, K. Desnos, and M. Abid, "Comparing Three Clustering-based Scheduling Methods for Energy-Aware Rapid Design of MP2SoCs," Journal of Signal Processing Systems, vol. 90, no. 4, pp. 537-570, Apr. 2018. <10.1007/s11265-017-1261-7>. <hal-01761220>.
ref_biblio
A. Mercat, F. Arrestier, M. Pelcat, W. Hamidouche, and D. Menard, "On predicting the HEVC intra quad-tree partitioning with tunable energy and rate-distortion," Journal of Real-Time Image Processing, 2018. <10.1007/s11554-018-0809-5>. <hal-01929171>.
ref_biblio
M. Pelcat, A. Mercat, K. Desnos, L. Maggiani, Y. Liu, J. Heulot, J.-F. Nezan, W. Hamidouche, D. Menard, and S. S. Bhattacharyya, "Reproducible Evaluation of System Efficiency with a Model of Architecture: From Theory to Practice," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 37, no. 10, pp. 2050 - 2063, 2018. <10.1109/TCAD.2017.2774822>. <hal-01646738>.

2017

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K. Abdelouahab, M. Pelcat, J. Sérot, C. Bourrasset, and F. Berry, "Tactics to Directly Map CNN graphs on Embedded FPGAs," IEEE Embedded Systems Letters, vol. 9, no. 4, pp. 113 - 116, 2017. <10.1109/LES.2017.2743247>. <hal-01626462>.
ref_biblio
S. Holmbacka, E. Nogues, M. Pelcat, S. Lafond, D. Menard, and J. Lilius, "Energy-Awareness and Performance Management with Parallel Dataflow Applications," Journal of Signal Processing Systems, vol. 87, no. 1, pp. 33--48, 2017. <10.1007/s11265-015-1059-4>. <hal-01228447>.
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R. Lazcano, D. Madronal, R. Salvador, K. Desnos, M. Pelcat, R. Guerra, H. Fabelo, S. Ortega, S. Lopez, G. M. Callico, E. Juarez, and C. Sanz, "Porting a PCA-based hyperspectral image dimensionality reduction algorithm for brain cancer detection on a manycore architecture," Journal of Systems Architecture, vol. 77, pp. 101-111, 2017. <10.1016/j.sysarc.2017.05.001>. <hal-01622064>.
ref_biblio
A. Mercat, J. Bonnot, M. Pelcat, K. Desnos, W. Hamidouche, and D. Menard, "Smart search space reduction for approximate computing: A low energy HEVC encoder case study," Journal of Systems Architecture, vol. 80, pp. 56-67, 2017. <10.1016/j.sysarc.2017.09.003>. <hal-01622380>.
ref_biblio
E. Nogues, J. Heulot, G. Herrou, L. Robin, M. Pelcat, D. Menard, E. Raffin, and W. Hamidouche, "Efficient DVFS for low power HEVC software decoder," Journal of Real-Time Image Processing, vol. 13, no. 1, pp. 39--54, 2017. <10.1007/s11554-016-0624-9>. <hal-01354629>.
ref_biblio
C. Sau, F. Palumbo, M. Pelcat, J. Heulot, E. Nogues, D. Menard, P. Meloni, and L. Raffo, "Challenging the Best HEVC Fractional Pixel FPGA Interpolators With Reconfigurable and Multifrequency Approximate Computing," IEEE Embedded Systems Letters, vol. 9, no. 3, pp. 65 - 68, Sep. 2017. <10.1109/LES.2017.2703585>. <hal-01667826>.

2016

ref_biblio
M. Ammar, M. Baklouti, M. Pelcat, K. Desnos, and M. Abid, "MDE-based Rapid DSE of multi-core embedded systems: The H.264 Decoder Case Study," Informacije Midem-journal of Microelectronics Electronic Components and Materials, vol. 46, no. 4, pp. 219--228, 2016. <hal-01502348>.
ref_biblio
K. Desnos, M. Pelcat, J. F. Nezan, and S. Aridhi, "On Memory Reuse Between Inputs and Outputs of Dataflow Actors," ACM Transactions on Embedded Computing Systems (TECS), vol. 15, no. 2, pp. 30, Feb. 2016. <10.1145/2871744>. <hal-01284333>.
ref_biblio
J. Mcallister, M. O’neill, and M. Pelcat, "Guest Editorial: New Frontiers in Signal Processing Applications and Embedded Processing Technologies," Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, May. 2016. <hal-01415970>.
ref_biblio
E. Nogues, D. Menard, and M. Pelcat, "Algorithmic-level Approximate Computing Applied to Energy Efficient HEVC Decoding," IEEE Transactions on Emerging Topics in Computing, Jul. 2016. <10.1109/TETC.2016.2593644>. <hal-01354638>.
ref_biblio
E. Raffin, E. Nogues, W. Hamidouche, S. Tomperi, M. Pelcat, and D. Menard, "Low Power HEVC Software Decoder for Mobile Devices," Journal of Real-Time Image Processing, vol. 12, no. 2, pp. 495--507, 2016. <10.1007/s11554-015-0512-8>. <hal-01334099>.
ref_biblio
Z. Zhou, W. Plishker, S. S. Bhattacharyya, K. Desnos, M. Pelcat, and J. F. Nezan, "Scheduling of Parallelized Synchronous Dataflow Actors for Multicore Signal Processing," Journal of Signal Processing Systems, Springer, vol. 83, no. 3, pp. 309--328, 2016. <10.1007/s11265-014-0956-2>. <hal-01075092>.

2014

ref_biblio
K. Desnos, M. Pelcat, J.-F. Nezan, and S. Aridhi, "Memory Analysis and Optimized Allocation of Dataflow Applications on Shared-Memory MPSoCs," Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, pp. 1-19, Sep. 2014. <10.1007/s11265-014-0952-6>. <hal-01083576>.

2009

ref_biblio
M. Pelcat, J. Piat, M. Wipliez, J. F. Nezan, and S. Aridhi, "An Open Framework for Rapid Prototyping of Signal Processing Applications," EURASIP Journal on Embedded Systems, vol. vol 2009, pp. 14, 2009. <hal-00429312>.

Conference papers

2018

ref_biblio
K. Abdelouahab, M. Pelcat, and F. Berry, "The Challenge of Multi-Operand Adders in CNNs on FPGAs: How Not to Solve It!," in 18th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS '18), Pythagorion, Greece, Jul. 2018, pp. 157-160. <10.1145/3229631.3235024>. <hal-01902952>.
ref_biblio
F. Arrestier, K. Desnos, M. Pelcat, J. Heulot, E. Juarez, and D. Menard, "Delays and States in Dataflow Models of Computation," in SAMOS XVIII, Pythagorion, Greece, Jul. 2018. <10.1145/3229631.3229645>. <hal-01850252>.
ref_biblio
J. Bonnot, K. Desnos, M. Pelcat, and D. Menard, "A Fast and Fuzzy Functional Simulator of Inexact Arithmetic Operators for Approximate Computing Systems," in GLSVLSI 2018, Chicago, United States, May. 2018. <10.1145/3194554.3194574>. <hal-01812719>.
ref_biblio
A. Mercat, F. Arrestier, M. Pelcat, W. Hamidouche, and D. Menard, "Machine Learning Based Choice of Characteristics for the One-Shot Determination of the HEVC Intra Coding Tree," in 2018 Picture Coding Symposium (PCS), San Francisco, France, Jun. 2018. <10.1109/PCS.2018.8456261>. <hal-01874891>.

2017

ref_biblio
E. M. Abdali, M. Pelcat, F. Berry, J.-P. Diguet, and F. Palumbo, "Exploring the Performance of Partially Reconfigurable Point-to-point Interconnects," in 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2017), Madrid, Spain, Jul. 2017. <10.1109/ReCoSoC.2017.8016160>. <hal-01629054>.
ref_biblio
K. Abdelouahab, M. Pelcat, and F. Berry, "PhD forum: Why TanH is a hardware friendly activation function for CNNs," in 11th International Conference on Distributed Smart Cameras, ICDSC 2017, Stanford, United States, Sep. 2017. <10.1145/3131885.3131937>. <hal-01687764>.
ref_biblio
K. E. Abdelouahab, M. Pelcat, J. Sérot, F. Berry, and J.-C. Quinton, "Direct Hardware Mapping of CNNs on FPGA-Based Smart Cameras," in Workshop on Architecture of Smart Cameras, Cordoba, Spain, Jun. 2017. <hal-01967273>.
ref_biblio
K. Abdelouahab, M. Pelcat, and F. Berry, "PhD Forum: Why TanH can be a Hardware Friendly Activation Function for CNNs," in Proceedings of the 11th International Conference on Distributed Smart Cameras - ICDSC 2017, Stanford, CA, United States, Sep. 2017. <hal-01654697>.
ref_biblio
A. Mercat, F. Arrestier, W. Hamidouche, M. Pelcat, and D. Menard, "Constrain the Docile CTUs: an In-Frame Complexity Allocator for HEVC Intra Encoders," in ICASSP2017, New Orleans, United States, Mar. 2017. <hal-01498495>.
ref_biblio
A. Mercat, F. Arrestier, W. Hamidouche, M. Pelcat, and D. Menard, "Energy Reduction Opportunities in an HEVC Real-Time Encoder," in ICASSP2017, New Orleans, United States, Mar. 2017. <hal-01498493>.
ref_biblio
A. Mercat, F. Arrestier, M. Pelcat, W. Hamidouche, and D. Menard, "Prediction of quad-tree partitioning for budgeted energy HEVC encoding," in 2017 IEEE International Workshop on Signal Processing Systems (SiPS), Lorient, France, Oct. 2017. <10.1109/SiPS.2017.8110025>. <hal-01689183>.
ref_biblio
A. Mercat, J. Bonnot, M. Pelcat, W. Hamidouche, and D. Menard, "Exploiting Computation Skip to Reduce Energy Consumption by Approximate Computing, an HEVC Encoder Case Study," in DATE, Lausanne, Switzerland, Mar. 2017. <hal-01498502>.
ref_biblio
N. Sidaty, J. Heulot, W. Hamidouche, M. Pelcat, and D. Menard, "Reducing Computational Complexity in HEVC Decoder for Mobile Energy Saving," in European Signal Processing Conference (EUSIPCO 2017), Nos Island, Greece, Aug. 2017. <hal-01580542>.
ref_biblio
L. Suriano, A. Rodriguez, K. Desnos, M. Pelcat, and E. De La Torre, "Analysis of a heterogeneous multi-core, multi-hw-accelerator-based system designed using PREESM and SDSoC," in 12th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip, ReCoSoC 2017, Madrid, Spain, Jul. 2017. <10.1109/ReCoSoC.2017.8016151>. <hal-01622393>.

2016

ref_biblio
E. Abdali, M. Pelcat, F. Berry, J.-P. Diguet, and D. Heller, "Task clustering approach to optimize the scheduling on a partially dynamically reconfigurable FPGAs for image processing algorithms," in 10th International Conference on Distributed Smart Cameras, ICDSC 2016, Paris, France, Sep. 2016, pp. 230--231. <10.1145/2967413.2974042>. <hal-01380635>.
ref_biblio
K. Abdelouahab, F. Berry, and M. Pelcat, "Propagation of Quantification Error Over Convolutional Neural Network layers: PhD Forum," in Proceedings of the 10th International Conference on Distributed Smart Camera, Paris, France, 2016, pp. 226--227. <hal-01626467>.
ref_biblio
K. E. Abdelouahab, C. Bourrasset, M. Pelcat, F. Berry, J.-C. Quinton, and J. Sérot, "A Holistic Approach for Optimizing DSP Block Utilization of a CNN implementation on FPGA," in Proceedings of the 10th International Conference on Distributed Smart Cameras - ICDSC'16, Paris, France, Sep. 2016. <hal-01415955>.
ref_biblio
M. Ammar, M. Baklouti, M. Pelcat, K. Desnos, and M. Abid, "Off-line DVFS integration in MDE-based design space exploration framework for MP2SoC systems," in 25th IEEE International Conference on Enabling Technologies: Infrastructure for Collaborative Enterprises, WETICE 2016, Paris, France, Jun. 2016, pp. 160--165. <10.1109/WETICE.2016.43>. <hal-01368137>.
ref_biblio
M. Ammar, M. Baklouti, M. Pelcat, K. Desnos, and M. Abid, "On Exploiting Energy-Aware Scheduling Algorithms for MDE-Based Design Space Exploration of MP2SoC," in 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP 2016), Heraklion, Greece, Feb. 2016, pp. 643-650. <10.1109/PDP.2016.110>. <hal-01305971>.
ref_biblio
S. Caux, E. Hendrickx, F. Berry, M. Pelcat, and J. Sérot, "Demo GPStudio: a toolchain for FPGA-based Smart Cameras: Demo Paper," in Proceedings of the 10th International Conference on Distributed Smart Camera, Unknown, Unknown Region, 2016, pp. 214--215. <hal-01626469>.
ref_biblio
M. Chavarrias, F. Pescador, M. Garrido, M. Pelcat, and E. Juarez, "Design of Multicore HEVC Decoders Using Actor-based Dataflow Models and OpenMP," in 2016 IEEE International Conference on Consumer Electronics, Las Vegas, United States, Jan. 2016. <hal-01239260>.
ref_biblio
K. Desnos, M. Pelcat, J.-F. Nezan, and S. Aridhi, "Distributed Memory Allocation Technique for Synchronous Dataflow Graphs," in 2016 IEEE International Workshop on Signal Processing Systems, Dallas, TX, United States, Oct. 2016. <10.1109/SiPS.2016.16>. <hal-01390486>.
ref_biblio
R. Lazcano, D. Madroñal, K. Desnos, M. Pelcat, R. Guerra, S. López, E. Juarez, and C. Sanz, "Parallelism Exploitation of a Dimensionality Reduction Algorithm Applied to Hyperspectral Images," in Conference on Design and Architectures for Signal and Image Processing (DASIP), Rennes, France, Oct. 2016. <hal-01415948>.
ref_biblio
R. Lazcano, I. Sidrach-Cardona, D. Madroñal, K. Desnos, M. Pelcat, E. Juárez, and C. Sanz, "Parallelism exploitation of a PCA algorithm for hyperspectral images using RVC-CAL," in High-Performance Computing in Geoscience and Remote Sensing VI, Edinburgh, United Kingdom, Sep. 2016. <10.1117/12.2241643>. <hal-01484535>.
ref_biblio
A. Mercat, W. Hamidouche, M. Pelcat, and D. Menard, "Estimating encoding complexity of a real-time embedded software HEVC codec," in Conference on Design and Architectures for Signal and Image Processing (DASIP), Rennes, France, Oct. 2016. <10.1109/DASIP.2016.7853792>. <hal-01498474>.
ref_biblio
E. Nogues, M. Pelcat, D. Menard, and A. Mercat, "Energy Efficient Scheduling of Real Time Signal Processing Applications through Combined DVFS and DPM," in 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP), Heraklion, Greece, Feb. 2016. <10.1109/PDP.2016.15>. <hal-01299607>.
ref_biblio
F. Palumbo, C. Sau, D. Evangelista, P. Meloni, M. Pelcat, and L. Raffo, "Runtime Energy versus Quality Tuning in Motion Compensation Filters for HEVC," in 14 th IFAC INTERNATIONAL CONFERENCE on PROGRAMMABLE DEVICES and EMBEDDED SYSTEMS (PDeS), Brno, Czech Republic, Oct. 2016. <hal-01415965>.
ref_biblio
M. Pelcat, K. Desnos, L. Maggiani, Y. Liu, J. Heulot, J. F. Nezan, and S. S. Bhattacharyya, "Models of Architecture: Reproducible Efficiency Evaluation for Signal Processing Systems," in International Workshop on Signal Processing Systems, Dallas, United States, Oct. 2016. <hal-01390508>.
ref_biblio
M. Pelcat, C. Bourrasset, L. Maggiani, and F. Berry, "Design Productivity of a High Level Synthesis Compiler versus HDL," in 2016 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS 2016), Agios Konstantinos, SAMOS, Greece, Jul. 2016. <10.1109/SAMOS.2016.7818341>. <hal-01358210>.
ref_biblio
E. Raffin, W. Hamidouche, E. Nogues, M. Pelcat, and D. Menard, "Scalable HEVC Decoder for Mobile Devices: Trade-offs between Energy Consumption and Quality," in Conference on Design and Architectures for Signal and Image Processing (DASIP), Rennes, France, Oct. 2016. <hal-01415938>.
ref_biblio
E. Raffin, W. Hamidouche, E. Nogues, M. Pelcat, and D. Menard, "Scalable HEVC decoder for mobile devices: Trade-off between energy consumption and quality," in 2016 Conference on Design and Architectures for Signal and Image Processing, DASIP 2016, Rennes, France, Oct. 2016, pp. 18--25. <10.1109/DASIP.2016.7853791>. <hal-01508042>.
ref_biblio
C. Sau, T. Fanni, P. Meloni, L. Raffo, M. Pelcat, and F. Palumbo, "Demo: Reconfigurable Platform Composer Tool," in 2016 Conference on Design and Architectures for Signal and Image Processing, DASIP 2016, Rennes, France, Oct. 2016, pp. 245--246. <10.1109/DASIP.2016.7853835>. <hal-01508049>.

2015

ref_biblio
K. Desnos, M. Pelcat, J.-F. Nezan, and S. Aridhi, "Buffer Merging Technique for Minimizing Memory Footprints of Synchronous Dataflow Specifications," in Acoustics, Speech and Signal Processing (ICASSP), 2015 IEEE International Conference on, Brisbane, Australia, Apr. 2015, pp. 1111-1115. <hal-01146340>.
ref_biblio
E. Nogues, E. Raffin, M. Pelcat, and D. Menard, "A modified HEVC decoder for low power decoding," in 12th ACM International Conference on Computing Frontiers, Ischia, France, May. 2015. <10.1145/2742854.2747284>. <hal-01157934>.
ref_biblio
E. Nogues, B. Romain, M. Pelcat, D. Menard, and E. Raffin, "A DVFS based HEVC decoder for energy-efficient software implementation on embedded processors," in IEEE International Conference on Multimedia and Expo (ICME), Torino, Italy, Jun. 2015. <10.1109/ICME.2015.7177406>. <hal-01184630>.
ref_biblio
E. Nogues, M. Lacour, E. Raffin, M. Pelcat, and D. Menard, "LOW POWER SOFTWARE HEVC DECODER DEMO FOR MOBILE DEVICES," in IEEE International Conference on Multimedia and Expo (ICME), Torino, Italy, Jun. 2015. <hal-01184523>.
ref_biblio
E. Nogues, E. Raffin, M. Pelcat, and D. Ménard, "Décodeur Video HEVC basse consommation," in XXVème colloque GRETSI, Lyon, France, Sep. 2015. <hal-01197057>.
ref_biblio
E. Raffin, W. Hamidouche, E. Nogues, M. Pelcat, D. Menard, and T. Seppo, "Energy Efficiency of a Parallel HEVC Software Decoder for Embedded Devices," in Computing Frontiers, Ischia, Italy, May. 2015, pp. 62:1--62:6. <10.1145/2742854.2747286>. <hal-01154295>.
ref_biblio
E. Raffin, E. Nogues, M. Lacour, M. Pelcat, D. Menard, K. Desnos, and J. F. Nezan, "Real-Time Low Power Software HEVC Decoder on Embedded GPP: A Side-by-Side Comparison," in Design and Architectures for Signal and Image Processing (DASIP), Cracow, Poland, Sep. 2015. <hal-01205912>.

2014

ref_biblio
M. Ammar, M. Baklouti, M. Pelcat, K. Desnos, and M. Abid, "MARTE to PiSDF transformation for data-intensive applications analysis," in Design & Architectures for Signal & Image Processing (DASIP), Madrid, Spain, Oct. 2014. <hal-01122725>.
ref_biblio
K. Desnos, S. El Assad, A. Arlicot, M. Pelcat, and D. Ménard, "Efficient Multicore Implementation of An Advanced Generator of Discrete Chaotic Sequences," in Chaos-Information Hiding and Security (CIHS), International Workshop on, London, United Kingdom, Dec. 2014. <hal-01094677>.
ref_biblio
J. Heulot, J. Menant, M. Pelcat, J.-F. Nezan, L. Morin, M. Pressigout, and S. Aridhi, "Demonstrating a Dataflow-based RTOS for Heterogeneous MPSoC by means of a Stereo Matching Application," in DASIP 2014, Madrid, Spain, Oct. 2014. <hal-01101788>.
ref_biblio
J. Heulot, M. Pelcat, J.-F. Nezan, Y. Oliva, S. Aridhi, and S. S. Bhattacharyya, "Just-In-Time Scheduling Techniques for Multicore Signal Processing Systems," in GlobalSIP14, Atlanta, United States, Dec. 2014. <hal-01101790>.
ref_biblio
J. Heulot, M. Pelcat, K. Desnos, J. F. Nezan, and S. Aridhi, "SPIDER: A Synchronous Parameterized and Interfaced Dataflow-Based RTOS for Multicore DSPs," in EDERC, Milan, Italy, Sep. 2014, pp. 167. <hal-01067052>.
ref_biblio
S. Holmbacka, E. Nogues, M. Pelcat, S. Lafond, and J. Lilius, "Energy Efficiency and Performance Management of Parallel Dataflow Applications," in The 2014 Conference on Design & Architectures for Signal & Image Processing, Madrid, Spain, Oct. 2014. <hal-01078573>.
ref_biblio
E. Nogues, S. Holmbacka, M. Pelcat, D. Menard, and J. Lilius, "Power-Aware HEVC Decoding with Tunable Image Quality," in IEEE International Workshop on Signal Processing Systems, Belfast, United Kingdom, Oct. 2014. <hal-01078566>.
ref_biblio
M. Pelcat, K. Desnos, J. Heulot, C. Guy, J. F. Nezan, and S. Aridhi, "PREESM: A Dataflow-Based Rapid Prototyping Framework for Simplifying Multicore DSP Programming," in EDERC, Italy, Sep. 2014, pp. 36. <hal-01059313>.

2013

ref_biblio
K. Desnos, M. Pelcat, J. F. Nezan, and S. Aridhi, "Pre- and post-scheduling memory allocation strategies on MPSoCs," in Electronic System Level Synthesis Conference (ESLSyn13), Austin, TX, United States, May. 2013, pp. 60-65. <hal-00868945>.
ref_biblio
K. Desnos, M. Pelcat, J.-F. Nezan, S. S. Bhattacharyya, and S. Aridhi, "PiMM: Parameterized and Interfaced dataflow Meta-Model for MPSoCs runtime reconfiguration," in 13th International Conference on Embedded Computer Systems: Architecture, Modeling and Simulation (SAMOS XIII), Samos, Greece, Jul. 2013, pp. 41 - 48. <10.1109/SAMOS.2013.6621104>. <hal-00877492>.
ref_biblio
J. Heulot, J. Boutellier, M. Pelcat, J. F. Nezan, and S. Aridhi, "Applying the Adaptive Hybrid Flow-Shop Scheduling Method to Schedule a 3GPP LTE Physical Layer Algorithm onto Many-Core Digital Signal Processors," in NASA/ESA Conference on Adaptive Hardware and Systems (AHS-2013), Turino, Italy, Jun. 2013, pp. Pages 123 - 129. <hal-00877643>.
ref_biblio
Z. Zhou, K. Desnos, M. Pelcat, J. F. Nezan, W. Plishker, and S. S. Bhattacharyya, "Scheduling of Parallelized Synchronous Dataflow Actors," in International Symposium on System-on-Chip 2013 (SoC), Tampere, Finland, Oct. 2013, pp. 10. <hal-00909324>.

2012

ref_biblio
K. Desnos, M. Pelcat, J. F. Nezan, and S. Aridhi, "Memory Bounds for the Distributed Execution of a Hierarchical Synchronous Data-Flow Graph," in 12th International Conference on Embedded Computer Systems: Architecture, Modeling and Simulation (SAMOS XII), Agios Konstantinos, Greece, Jul. 2012, pp. 160. <hal-00721335>.
ref_biblio
J. Heulot, K. Desnos, J. F. Nezan, M. Pelcat, M. Raulet, H. Yviquel, P.-L. Lagalaye, and J.-C. Le Lann, "AN EXPERIMENTAL TOOLCHAIN BASED ON HIGH-LEVEL DATAFLOW MODELS OF COMPUTATION FOR HETEROGENEOUS MPSOC," in DASIP, Karlsruhe, Germany, Oct. 2012, pp. xx. <hal-00749175>.

2011

ref_biblio
Y. Oliva, M. Pelcat, J. F. Nezan, J.-C. Prévotet, and S. Aridhi, "Building a RTOS for MPSoC Dataflow Programming," in 2011 International Symposium on System on Chip (SoC), Finland, Oct. 2011, pp. 143. <hal-00658848>.

2010

ref_biblio
M. Pelcat, J. F. Nezan, and S. Aridhi, "Adaptive Multicore Scheduling for the LTE Uplink," in NASA/ESA Conference on Adaptive Hardware and Systems (Ahs 2010), Anaheim, United States, Jun. 2010. <hal-00488576>.

2009

ref_biblio
M. Pelcat, P. Menuet, S. Aridhi, and J. F. Nezan, "A STATIC SCHEDULING FRAMEWORK FOR DEPLOYING APPLICATIONS ON MULTICORE ARCHITECTURES," in Parallel and Distributed Computing and Networks (PDCN), Innsbruck, Austria, Feb. 2009, pp. 6 ages. <hal-00429408>.
ref_biblio
M. Pelcat, P. Menuet, J. F. Nezan, and S. Aridhi, "Scalable Compile-Time Scheduler for Multi-core Architectures," in Design, Automation and Test in Europe, DATE 2009, Nice, France, Apr. 2009, pp. 1552-1555. <hal-00429393>.
ref_biblio
M. Pelcat, J. F. Nezan, J. Piat, J. Croizer, and S. Aridhi, "A System-Level Architecture Model for Rapid Prototyping of Heterogeneous Multicore Embedded Systems," in Conference on Design and Architectures for Signal and Image Processing (DASIP) 2009, nice, France, Sep. 2009, pp. 8 ages. <hal-00429397>.
ref_biblio
J. Piat, S. S. Bhattacharyya, M. Pelcat, and M. Raulet, "Multi-Core Code Generation From Interface Based Hierarchy," in Conference on Design and Architectures for Signal and Image Processing (DASIP) 2009, Sophia Antipolis, France, Sep. 2009, pp. online. <hal-00440479>.

2008

ref_biblio
M. Pelcat, S. Aridhi, and J. F. Nezan, "Optimization of automatically generated multi-core code for the LTE RACH-PD algorithm," in DASIP 2008, Bruxelles, Belgium, Nov. 2008, pp. . <hal-00336477>.
ref_biblio
J. Piat, M. Raulet, M. Pelcat, P. Mu, and O. Déforges, "An extensible framework for fast prototyping of multiprocessor dataflow applications," in Design and Test Workshop, 2008. IDT 2008. 3rd International, Tunisia, 2008, pp. 215--220. <10.1109/IDT.2008.4802500>. <hal-00398830>.

2007

ref_biblio
M. Pelcat, M. Blestel, and M. Raulet, "From AVC Decoder to SVC: Minor Impact on a Dataflow Graph Description," in Picture Coding Symposium (PCS 2007), France, Nov. 2007, pp. 1067. <hal-00180103>.

Book sections

2017

ref_biblio
M. Pelcat, "Models of Architecture for DSP Systems," in Handbook of Signal Processing Systems, 2017. <hal-01660620>.

2016

ref_biblio
M. Ammar, M. Baklouti, M. Pelcat, K. Desnos, and M. Abid, "Automatic Generation of S-LAM Descriptions from UML/MARTE for the DSE of Massively Parallel Embedded Systems," in Software Engineering, Artificial Intelligence, Networking and Parallel/Distributed Computing 2015 (Studies in Computational Intelligence), Springer, 2016, pp. 195-211. <10.1007/978-3-319-23509-7\_14>. <hal-01252511>.

2012

ref_biblio
M. Babel, F. Pasteau, C. Strauss, M. Pelcat, L. Bédat, M. Blestel, and O. Déforges, "Preserving data integrity of encoded medical images: the LAR compression framework," in Advances in Reasoning-Based Image Processing Intelligent Systems, Springer, Jan. 2012, pp. 1-35. <hal-00658130>.

Habilitation à diriger des recherches

2017

ref_biblio
M. Pelcat, "Models, Methods and Tools for Bridging the Design Productivity Gap of Embedded Signal Processing Systems," H.D.R. dissertation, Université Clermont Auvergne, Jul. 2017. <tel-01610096>.

Other publications

2015

ref_biblio
E. Nogues, E. Raffin, M. Pelcat, and D. Menard, "HEVC Decoding with Tunable Image Quality - Subjective evaluation," unpublished, Feb. 2015. <hal-01119964>.
ref_biblio
E. Raffin, E. Nogues, M. Pelcat, and D. Menard, "HEVC Decoding with Tunable Image Quality - Power saving and complexity reduction," unpublished, Feb. 2015. <hal-01119961>.
ref_biblio
E. Raffin, M. Lacour, E. Nogues, M. Pelcat, D. Menard, and Y. Liu, "Detailed Evaluation of Tunable Image Quality HEVC Decoding," unpublished, Jun. 2015. <hal-01205921>.

2014

ref_biblio
E. Nogues, X. Ducloux, E. Raffin, M. Pelcat, and D. Menard, "HEVC Decoding with Tunable Image Quality for Green Metadata applications," unpublished, Oct. 2014. <hal-01119966>.

2008

ref_biblio
F. Decologne, M. Blestel, M. Raulet, and M. Pelcat, "M15432: Specific Functional Units for SVC: Textual description and CAL implementation,," unpublished, Apr. 2008. <hal-00689928>.

2007

ref_biblio
M. Pelcat, M. Raulet, O. Déforges, M. Blestel, and J. F. Nezan, "M14965: Implementing SVC from RVC AVC: description of the specific SVC FUs," unpublished, Nov. 2007. <hal-00696462>.
ref_biblio
M. Pelcat, M. Blestel, M. Raulet, J. F. Nezan, and O. Déforges, "M14463: Evolutions of RVC so as to handle SVC decoding," unpublished, Apr. 2007. <hal-00696461>.
ref_biblio
M. Raulet, M. Pelcat, and M. Blestel, "M14655: From AVC to SVC: minor and major modifications in a RVC decoder implementation," unpublished, 2007. <hal-00696468>.
ref_biblio
G. Roquier, M. Pelcat, M. Raulet, M. Wipliez, J. F. Nezan, and O. Déforges, "M14457: A scheme for implementing MPEG-4 SP codec in the RVC framework," unpublished, Apr. 2007. <hal-00696464>.

Books

2012

ref_biblio
M. Pelcat, S. Aridhi, J. Piat, and J. F. Nezan, Physical Layer Multi-Core Prototyping: A Dataflow-Based Approach for LTE eNodeB (Lecture Notes in Electrical Engineering), Springer-Verlag London, Aug. 2012, pp. 224. <10.1007/978-1-4471-4210-2>. <hal-00739957>.

Patents

2014

ref_biblio
E. Nogues, D. Menard, M. Pelcat, and E. Raffin, "DECODER, METHOD AND SYSTEM FOR DECODING MULTIMEDIA STREAMS," France Patent WO2016059196, Oct. 2014. <hal-01354642>.

Reports

2017

ref_biblio
K. Abdelouahab, M. Pelcat, J. Sérot, F. Berry, C. Bourrasset, and J.-C. Quinton, "Hardware Automated Dataflow Deployment of CNNs," unpublished, 2017. <hal-01626460>.
ref_biblio
K. Abdelouahab, M. Pelcat, J. Sérot, F. Berry, C. Bourrasset, and J.-C. Quinton, "Hardware Automated Datafow Deployment of CNNs," unpublished, May. 2017. <hal-01519524>.
ref_biblio
M. Dejean-Servières, K. Desnos, K. Abdelouahab, W. Hamidouche, L. Morin, and M. Pelcat, "Study of the Impact of Standard Image Compression Techniques on Performance of Image Classification with a Convolutional Neural Network," unpublished, Dec. 2017. <hal-01725126>.
ref_biblio
M. Pelcat, A. Mercat, K. Desnos, L. Maggiani, Y. Liu, J. Heulot, J.-F. Nezan, W. Hamidouche, D. Menard, and S. S. Bhattacharyya, "Models of Architecture: Application to ESL Model-Based Energy Consumption Estimation," unpublished, Feb. 2017. <hal-01464856>.

2015

ref_biblio
M. Pelcat, K. Desnos, L. Maggiani, Y. Liu, J. Heulot, J.-F. Nezan, and S. S. Bhattacharyya, "Models of Architecture," unpublished, Dec. 2015. <hal-01244470>.

Theses

2010

ref_biblio
M. Pelcat, "Rapid Prototyping and Dataflow-Based Code Generation for the 3GPP LTE eNodeB Physical Layer mapped onto Multi-Core DSPs," M.S. thesis, INSA de Rennes, Sep. 2010, no. 2010ISAR0011. <tel-00578043>.

Preprints, Working Papers, ...

2018

ref_biblio
K. Abdelouahab, M. Pelcat, F. Berry, and J. Sérot, "Accelerating CNN inference on FPGAs: A Survey," unpublished, Mar. 2018. <hal-01695375>.