Team of ISPR

  • RFSM is a set of tools aimed at describing, drawing and simulating reactive finite state machines (FSMs). Reactive FSMs are a FSMs for which transitions can only take place at the occurence of events.

    RFSM has been developed mainly for pedagogical purposes, in order to initiate students to model-based design. It is currently used in courses dedicated to embedded system design both on software and hardware platforms (microcontrolers and FPGA resp.). But RFSM can also be used to generate code (C, SystemC or VHDL) from high-level models to be integrated to existing applications.

  • Haddoc2 is a tool to automatically design FPGA-based hardware accelerators for convolutional neural networks (CNNs). Using a Caffe model, Haddoc2 generates a hardware description of the network (in VHDL-2008) which is constructor and device independent. Haddoc2 is built upon the principals of Dataflow stream-based processing of data, and, implements CNNs using a Direct Hardware Mapping approach, where all the actors involved in CNN processing are physically mapped on the FPGA.
  • CAPH is a domain-specific  language for describing and implementing stream-processing applications on reconfigurable hardware, such as FPGAs. CAPH generates VHDL code from high-level descriptions of signal or image processing applications. CAPH relies upon the actor/dataflow model of computation. Applications are described as networks of purely dataflow actors exchanging tokens through unidirectional channels and the behavior of each actor is defined as a set of transition rules using pattern matching.
  • INAOE/DREAM Benchmark dataset is an odometry benchmark which consists of 130 monocular sequences provided with ground truth trajectories for all the sequences. The data was recorded at full frame rate (60 Hz) and, the ground-truth trajectory was obtained from a high-accuracy motion-capture system with eight high-speed tracking cameras (100 Hz).
      • can describe hierarchical and/or parameterized graphs
      • support two styles of description : structural and functional
      • use polymorphic type inference to check graphs
      • supports the notion of higher order wiring functions for describing and encapsulating graph patterns
      • supports several dataflow semantics (SDF, PSDF, ..) by means of annotations
The generated code is independent of the target implementation platform (software, hardware, mixed, ..). Targeting is done using dedicated backends. The current version comes is equipped with five backends :
      • a DOT backend for visualisation of the generated networks
      • a SystemC backend for simulation
      • a PREESM backend for implementing the described dataflow applications on many/multi-core embedded platforms
      • a DIF backend for interfacing to various dataflow analysis tools
      • an XDF backend for interfacing to CAL-based design flows
HoCL is a joint project between the Dream and Vaader research groups.