Visual Odometry Algorithm and Architecture for FPGA Acceleration - DREAM - A team of ISPR

Visual Odometry Algorithm and Architecture for FPGA Acceleration

Research group on Embedded Architecture for Multisensing

Camera pose estimation across video sequences is an important issue under several computer vision applications. In previous work, the most popular approach consists on optimization techniques applied over 2D/3D point correspondences for two consecutive frames from a video sequence. Unfortunately, these optimization techniques are iterative and depend on nonlinear optimizations applied over some geometric constraint. For real-time embedded applications, another approach, more efficient in terms of computational size and cost, could be a linear or closed-form solution for the camera pose estimation problem. In this work, we propose a new camera pose estimation approach where 2D pixel displacements are used as linear/dependent parameters for the camera pose estimation. Unlike previous work, camera poses are estimated without iterative behavior and without geometric constraints. As a results, our FPGA architecture delivers accurate/fast estimations (x50 faster than previous algorithms based on optimization techniques) for synthetic data and real world scenarios.

 

Fig. 1 The developed FPGA architecture

Padawan DREAM